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| Integrated Circuit Systems, Inc. ICS9248-80 General Purpose 133MHz System Clock General Description The ICS9248-80 is a general purpose system clock. It provides 8 output CLKs, 1 REF CLK and excellent power management features through CLK_STOP#. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-80 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Features Extended temperature range (-20C to +70C) Output features: - 8 CLK outputs @ 3.3V, up to 133.34MHz. - 1-REF output @ 3.3V, 14.31818MHz. Spread Spectrum for EMI control I2C interface to stop clocks, select spread and frequency. Excellent power managment feature through CLK_STOP# and individual stop clocks through I2C. Input is from a 14.31818MHz crystal. Block Diagram Pin Configuration 28-Pin 209 mil SSOP * These inputs have a 120K internal pull-up to 3.3V. ** These inputs have a 120K internal pull-down to GND. Pentium II is a trademark of Intel Corporation I2C is a trademark of Philips Corporation 9248-80 Rev A 3/21/00 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-80 Pin Descriptions Pin number 1 2 3 4 5 6, 7, 14, 27 8, 11 9, 18, 24 10 12 13 15, 21 16, 17, 19, 20, 22, 23, 25, 26 28 Pin name REF GNDREF X1 X2 VDD FS (0:3) GND VDDO CLK_STOP# SDATA SCLK GNDO CLK (0:7) VDDREF Type OUT PWR IN OUT PWR IN PWR PWR IN IN IN PWR OUT PWR Description 14.318MHz reference clock outputs at 3.3V Gnd pin for REF clocks XTAL_IN 14.318MHz crystal input XTAL_OUT Crystal output 3.3V power input Logic - input for frequency selection Ground 3.3V power for CLK outputs Stops all clock outputs Data input for I C serial input. Clock input of I C input Ground for CLK outputs Clock outputs up to 133.34MHz Power pin for REF clocks 2 2 Frequency Selection FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLK (MHz) 133.34 125.01 120.00 114.99 109.99 105.00 100.00 95.00 90.00 85.01 75.00 70.00 66.67 60.00 54.99 33.33 2 ICS9248-80 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver) ACK ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 3 ICS9248-80 Byte 0: Functionality and frequency select register (Default=0) (1 = Running, 0 = Stopped Low) Bit Bit7 Description 0: 0 to -0.5% down spread 1: 0 to -1.0% down spread Bits 2 0 0 0 0 0 0 Bit (2, 6:4) 0 0 1 1 1 1 1 1 1 1 Bit3 Bit1 Bit0 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLK frequency 133.34 125.01 120.00 114.99 109.99 105.00 100.00 95.00 91.00 85.01 75.00 70.00 66.67 60.00 54.99 33.33 0 0 0 Note 1 PWD 0 0: Frequency is selected by hardware FS(0:3) 1: frequency is selected by bits 2, 6:4 of I2C 0: Normal 1: Spread 0: Outputs running 1: Outputs tri-stated Notes: 1. Default is for frequency control thru hardware pins. Byte 1: CLK output control register (1 = Running, 0 = Stopped Low) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 16 17 19 20 22 23 25 26 PWD 1 1 1 1 1 1 1 1 Description CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 CLK0 4 ICS9248-80 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 20C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = -20C - +70 C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time1 Clk Stabilization 1 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD2.5OP Fi CIN CINX TTrans TS TSTAB CONDITIONS MIN 2 VSS-0.3 -5 -200 TYP VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66 MHz VDD = 3.3 V; Logic Inputs X1 & X2 pins To first crossing of target Freq. From first crossing to 1% of target Freq. From VDD = 3.3 V to 1% target Freq. 0.1 2.0 -100 50 14.318 6 1.3 0.3 <3 MAX UNITS VDD+0.3 V 0.8 V A 5 A A 100 5 2 3 mA MHz pF pF ms ms ms Guaranteed by design, not 100% tested in production. 5 ICS9248-80 Electrical Characteristics - CLK TA = -20C - +70 C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew 1 SYMBOL VOH3 VOL3 IOH3 IOL3 Tr3 1 Tf3 Dt3 1 1 CONDITIONS IOH = -1 mA IOL = 1 mA VOH@Min = 1.0 V,VOH@Max = 2375 V VOL@Min = 1.2 V,VOL@Max = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V MIN 2 -27 27 TYP MAX UNITS V 0.4 V 27 mA 30 mA 1.33 1.4 ns ns % ps ps ps 45 55 58 250 250 250 Jitter, cyc-cyc Jitter, Absolute 1 1 Tsk1 tjcyc tjabs1 Guarenteed by design, not 100% tested in production. 6 ICS9248-80 Country of origin location and ejector pin on package bottom is optional and depends on assembly location. Pin 1 D/2 Index Area E1 /2 PARTING LINE E L DETAIL "A" BOTTOM VIEW e A2 SEE DETAIL "A" c b A .004 C TOP VIEW E1 D END VIEW SIDE VIEW A1 SEATING PLANE -C- SYMBOL MIN. A A1 A2 b c D E1 e E L N 0.002 0.065 0.009 0.004 0.197 0.291 0.022 0 COMMON DIMENSIONS NOM. 0.069 0.012 See Variations 0.209 0.0256 BSC 0.307 0.030 See Variations 4 MAX. 0.078 0.073 0.015 0.010 0.220 0.323 0.037 8 VARIATIONS N 14 16 20 24 28 30 MIN. 0.232 0.232 0.272 0.311 0.390 0.390 D NOM. 0.244 0.244 0.284 0.323 0.402 0.402 MAX. 0.256 0.256 0.295 0.335 0.413 0.413 Dimensions in inches 209 mil SSOP Package Ordering Information ICS9248yF-80-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 7 |
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